A reproduced signal output from a digital information reproducing device such as an optical disk device is represented by a digital value. In order to extract reproduced data from such a reproduced signal, it is necessary to extract the bit structure of the reproduced data by synchronization with a reference clock.
The reference clock is typically generated by a PLL (Phase Locked Loop) circuit, and directed to a digital processing circuit such as a decoding circuit. The above-mentioned PLL circuit is not only used for such data reproduction, but also adopted for various applications. For example, the PLL circuit is used for maintaining clocks input to a plurality of circuits in an integrated circuit in synchronization, and for frequency tuning or as a detection circuit in communication device.
In particular, the PLL circuit used for data reproduction is called a data PLL circuit, and the reproduced signal is represented by a continuous rectangular pulse train of a width which is an integer multiple of a reference clock. Therefore, by inputting the reproduced signal, the extraction of the reference clock of the reproduced signal and the synchronization of the reference clock and the reproduced signal are performed simultaneously.
FIG. 11 is a block diagram showing a schematic structure of a conventional data PLL circuit. A conventional data PLL circuit 100 shown in FIG. 11 includes a phase comparator circuit 101, a frequency comparator circuit 102, charge pumps (CP) 103 and 104, a low-pass filter (LPF) 105, and a voltage control oscillator (VCO) 106.
The phase comparator circuit 101 shown in FIG. 11 compares the leading edge of input data PLDT which is equivalent to the above-mentioned reproduced signal and the leading edge of an oscillation clock PLCK output from the voltage control oscillator 106. When the leading edge of the oscillation clock PLCK is delayed with respect to the input data PLDT, the phase comparator circuit 101 inputs a signal PLCPP as a low level signal "L" to the charge pump 104 during that period.
On the other hand, when the leading edge of the oscillation clock PLCK is ahead of the input data PLDT, the phase comparator circuit 101 inputs a signal PLCPN as a high level signal "H" to the charge pump 104 during that period.
In other words, the phase comparator circuit 101 is a circuit that outputs a signal for reducing the frequency of the clock PLCK when the phase of the oscillation clock PLCK is ahead of the input data PLDT and outputs a signal for increasing the frequency of the clock PLCK when the phase of the oscillation clock PLCK is delayed with respect to the input data PLDT, and inputs these signals to the charge pump 103 in the later stage.
Similarly, the frequency comparator circuit 102 is a circuit that outputs a signal for reducing the frequency of the oscillation clock PLCK when the frequency of the oscillation clock PLCK is higher than that of the input data PLDT and outputs a signal for increasing the frequency of the oscillation clock PLCK when the frequency of the oscillation clock PLCK is lower than that of the input data PLDT, and inputs these signals to the charge pump 104 in the later stage.
For instance, each of the charge pumps 103 and 104 is constructed such that a current source for supplying positive charge (hereinafter referred to as the positive current source), a P-channel MOS transistor, an N-channel MOS transistor, and a current source for supplying negative charge (hereinafter referred to as the negative current source) are sequentially connected in series between the power supply and the ground. The node of the P-channel MOS transistor and the N-channel MOS transistor (node N) is connected to an input section of a low-pass filter 105 in the next stage.
According to this structure, the above-mentioned signal PLCPP is input to the gate of the P-channel MOS transistor, and the signal PLCPN is input to the gate of the N-channel MOS transistor. Furthermore, the output sections of the charge pumps 103 and 104 are connected to each other, and the output currents of the charge pumps are added together and input to the low-pass filter 105 in the next stage.
When the signal PLCPP representing a low level is input to the charge pumps 103 and 104 having such a structure, the P-channel MOS transistor turns into an ON state, and a positive charge is supplied to the node N from the positive current-source. More specifically, the low-pass filter 105 is supplied with the positive charge of a quantity obtained by integrating the current value of the positive current source over a period of time in which the signal PLCPP has a low level.
On the other hand, when the signal PLCPN representing a high level is input, the N-channel MOS transistor turns into an ON state, and a negative charge is supplied to the node N from the negative current source. More specifically, the low-pass filter 105 is supplied with the negative charge of a quantity obtained by integrating the current value of the negative current source over a period of time in which the signal PLCPN has a high level.
For example, the low-pass filter 105 is constructed by connecting a resistor and a capacitor in series between the node of the charge pumps 103 and 104 and the ground. This low-pass filter accumulates the charges supplied from the charge pumps 103 and 104 in the capacitor through the resistor, and removes harmonic components and generates a control voltage for controlling the voltage control oscillator 106 in the next stage.
The voltage control oscillator 106 is an oscillator which is supplied with the control voltage generated by the low-pass filter 105, and outputs the oscillation clock PLCK of an oscillation frequency which is determined by the input control voltage. This oscillation clock PLCK is a reference clock used as a synchronizing signal for the reproduced data. Further, the oscillation clock PLCK is input to the phase comparator circuit 101 and frequency comparator circuit 102, thereby forming a negative feedback loop.
With the function of the negative feedback, the oscillation clock PLCK coincides (is locked) with the frequency and phase of the input data PLDT, thereby allowing extraction of a reference clock synchronized with the input data PLDT from the input data PLDT.
Incidentally, in the data PLL circuit 100 shown in FIG. 11, the charge pumps 103 and 104 and the low-pass filter 105 can be achieved equivalently by digital circuits. Besides, all of the structures including these members, the phase comparator circuit 101, frequency comparator circuit 102, and voltage control oscillator 106 can be changed into digital form.
FIG. 12 is a circuit diagram showing the internal structure of the phase comparator circuit 101. As illustrated in FIG. 11, the phase comparator circuit 101 includes four D-type flip-flops F111 to F114, an EOR gate G111, an AND gate G112, andaninverterG113. Meanwhile, FIG. 13 is a timing chart for explaining the operation of the phase comparator circuit 101 and the operation of the above-mentioned data PLL circuit 100.
Referring now to FIGS. 12 and 13, the following description will explain an operation in the phase comparator circuit 101, and an operation of the data PLL circuit 100 associated with the operation of the phase comparator circuit is 101.
First, the input data PLDT is input to one of the input terminals of the EOR gates G111. Since an inverted output (Q) of the D-type flip-flop F112 is input to the other input terminals of the EOR gate G111, the EOR gate G111 outputs a signal "H" representing a high level when the logical level of the input data PLDT and the logical level indicated by the inverted output of the D-type flip flop F112 differ from each other.
Here, the signal output from the EOR gate is input to the D-type flip-flop F111 as the clock input (T), and a data input (Q) of the D-type flip-flop F111 is pulled up to a high level. Accordingly, the high-level signal "H" output from the EOR gate G111 is latched by the D-type flip-flop F111.
Moreover, the D-type flip-flop F111 outputs an inverted output (Q) as the signal PLCPP. In the above-mentioned state, the signal PLCPP indicates a low-level signal "L".
The D-type flip-flop F112 is supplied with its inverted output (Q) as data input (D) and the data output (Q) of the D-type flip-flop F111 as the clock input (T). Therefore, when the D-type flip-flop F111 latches "H" as described above, the D-type flip-flop F112 inverts the value of the logical level held until then.
Consequently, the logical level indicated by the inverted output (Q) of the D-type flip-flop F112 and the logical level of the input data PLDT are equal to each other, and the output of the EOR gate G111 changes into a signal "L" representing a low level.
Besides, the D-type flip-flop F113 is supplied with the data output (Q) of the D-type flip-flop F111 as the data input (Q) and the oscillation clock PLCK as the clock input (T). Therefore, in the above-mentioned state in which the D-type flip-flop F111 latches "H", the D-type flip-flop F113 latches "H" with the leading edge of the oscillation clock PLCK.
Furthermore, since the inverted output (Q) of the D-type flip-flop F113 is input to a reset terminal (inverted input) of the D-type flip-flop F111, when the D-type flip-flop F111 lathes "H", the D-type flip-flop F111 is reset.
The D-type flip-flop F114 is supplied with the data output (Q) of the D-type flip-flop F113 as the data input (D) and the output of the inverter G113 as the clock input (T). Since the inverter G113 inverts and outputs the input oscillation clock PLCK, the D-type flip-flop F114 lathes "H" as the data output (Q) of the D-type flip-flop F113 with the trailing edge of the oscillation clock PLCK.
The data output (Q) of the flip-flop F113 and the data output (Q) of the D-type flip-flop F114 are input to the AND gate G112. The AND gate G112 outputs its output as the signal PLCPN, and the signal PLCPN indicates a high level "H" when the logical levels of the input signals both indicate "H".
With the above-explained operation, the signal PLCPP output from the phase comparator circuit 101 indicates a low-level signal "L" in a period that starts with the latching of "H" by the D-type flop-flop F111 by a change of the input data PLDT and ends with the reset by the inverted output (Q) of the D-type flip-flop F113. On the other hand, when both of the data output (Q) of the D-type flip-flop F113 and the data output (Q) of the D-type flip-flop F114 are "H", the signal PLCPN indicates a high-level signal "H".
More specifically, as illustrated in FIG. 13, the signal PLCPP represents "L" in a period between the leading edge or the trailing edge of the input data PLDT and the trailing edge of the next oscillation clock PLCK. During the period when the signal PLCPP is "L", the charge pump 103 supplies a positive charge to the low-pass filter 105, and increases the control voltage to be input to the voltage control oscillator 106 as shown in FIG. 13 (the timing chart of the LPF in FIG. 13).
On the other hand, as illustrated in FIG. 13, the signal PLCPN represents "H" in a period between the leading edge of the signal PLCPP and the trailing edge of the next oscillation clock PLCK. During the period when the signal PLCPN is "H", the charge pump 103 supplies a negative charge to the low-pass filter 105, and decreases the control voltage to be input to the voltage control oscillator 106 as shown in FIG. 13 (the timing chart of the LPF in FIG. 13).
In particular, the above-described phase comparator circuit 101 is operated so as to synchronize the trailing edge of the oscillation clock PLCK with the leading edge or the trailing edge of the input data PLDT, and the signals PLCPP and PLCPN of the phase comparator circuit 101 have a uniform pulse width when the phase difference between the input data PLDT and oscillation clock PLCK is zero.
The conventional data PLL circuit 100 is configured as explained above, and operates so as to minimize the frequency difference and phase difference between the input data PLDT and the oscillation clock PLCK of the voltage control oscillator 106.
However, as illustrated in FIG. 13, even when the phase difference between the input data PLDT and the oscillation clock PLCK is zero, the phase comparator circuit 101 constituting the conventional data PLL circuit 100 outputs the signals PLCPP and PLCPN whose pulse widths are equal to each other. Therefore, the increase/decrease of the control signal resulting from these signals PLCPP and PLCPN causes the jitter in the oscillation clock to increased jitter.
Moreover, due to the delay of the gates constituting the data PLL circuit 100 and the unbalance between the currents supplied from the positive current source and negative current source in the charge pumps 103 and 104, the locked state is sometimes deviated from an ideal phase-locked state. In the conventional data PLL circuit 100, since the locked state is uniformly determined by the circuit structure, it is difficult to set an offset for resetting the deviation of the locked state.